1. Field of the Invention
The present invention relates to multi-gigabit transceivers (MGTS) located on a programmable logic device (PLD), such as a field programmable gate array (FPGA). More specifically, the present invention relates to a method and apparatus for providing low jitter clock signals for use in the operation of an MGT on a PLD.
2. Related Art
FIG. 1 is a simplified block diagram of a portion of a conventional multi-gigabit transceiver (MGT) 100. The illustrated elements of MGT 100 include serializer 101, deserializer 102 and transmit phase locked loop (PLL) 111. It is understood by those of ordinary skill that conventional MGT 100 includes many other elements in addition to those illustrated in FIG. 1.
In general, MGT 100 operates as an input/output (I/O) interface between serial channel 121 and parallel channel 122. Thus, parallel data (N-bits wide in the described example) is provided to serializer 101 at a first frequency. For example, 20-bit data values can be provided to serializer 101 in response to a reference clock signal CREF having a frequency of 156.25 MHz. Transmit PLL 111 generates a clock signal CTX having a frequency N/2 times greater than the reference clock signal CREF. Thus, in the described example, clock signal CTX has a frequency ten times greater than CREF, or 1.5625 GHz. Note that the feedback clock signal provided to transmit PLL 111 is not shown in FIG. 1. Serializer 101 serializes the 20-bit input data values using multiplexed timing in response to the clock signal CTX, thereby providing a serial differential output data stream at a data rate of 3.125 gigabits per second (Gbps). Note that a serial differential data stream consists of 2 signals.
Similarly, deserializer 102 receives a serial differential input data stream at a data rate of 3.125 Gbps. Deserializer 102 samples the serial differential input data stream at the frequency of the CREF signal, thereby providing a 20-bit wide parallel output data stream at a frequency of 156.25 MHz.
The quality of the reference clock signal CREF determines the operational bandwidth of MGT 100. As the jitter present in the reference clock signal CREF increases, the accuracy of the clock signal CTX generated by transmit PLL 111 decreases, thereby reducing the operational bandwidth of MGT 100. For example, reference clock CREF must exhibit jitter of 40 picoseconds peak-to-peak or less to allow MGT 100 to operate at a data rate range of 500 Mbps to 3.125 Gbps. MGT 100 would be limited to smaller frequency ranges when using reference clock signals exhibiting greater jitter.
Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), have not previously included MGTs. One reason for this is that the clock routing systems used by PLDs do not typically provide clock signals having jitter low enough to support multi-gigabit operation. The clock signals used by the I/O circuitry of PLDs typically have a significant amount of jitter based on the fact that these clock signals are typically stepped down from a relatively high I/O voltage (e.g., a 2.5 Volt level) to a relatively low core voltage (e.g., a 1.5 Volt level), and then stepped back up to the relatively high I/O voltage level. These stepping down and stepping up processes add an unacceptable amount of jitter to the clock signals.
It would therefore be desirable to have a novel clocking scheme in a programmable logic device capable of supporting multi-gigabit transceivers.